Lecturer Profile |
Quan Pan (S’08–M’14) received the Ph.D. degree in electronics and computer engineering from the Hong Kong University of Science and Technology, Hong Kong, China, in 2014. He is an Assistant Professor and Ph.D supervisor now in School of Microelectronics, Southern University of Science and Technology (SUSTech). His current research interests include high-speed analog/RF IC designs, which include Wireline/Wireless high-speed communication ICs (both receiver and transmitter), Serdes/clock and recovery (CDR) circuits, mm-wave IC, GaN IC, Si-Photonics. He has published multiple high-quality journals/conference papers, and he has more than 8-year industry experience, including 4-year state-of-the-art industry experience in Silicon Valley IC startup. With the team, he successfully silicon-proved 200-GbE optical and copper interconnect physical layer transceivers for Hyperscale & Enterprise Data Centers from 2015 to 2018 with a series of chips in 28nm/16nm/12nm CMOS technologies, respectively. He is also the recipient of 2017 IEEE Circuits and Systems Society Outstanding Young Author Award. |
Lecture Abstract |
Complementary metal-oxide-semiconductor (CMOS) optoelectronic integrated circuits (OEICs) have become extremely attractive since they are extensively adopted in optical communications, such as local area networks, board-to-board, and data center-to-data centers. Currently energy-efficient 100-Gbit Ethernet (100-GbE) systems based on four channels of 25-Gb/s links requiring an optical receiver and a clock data recovery circuit with sophisticated equalization are implemented. Future 200/400-GbE PAM4 systems are also studied. |
